The present invention relates to a semiconductor structure applicable to semiconductor devices, such as a MOSFET (an insulated gate field effect transistor), an IGBT (an insulated gate bipolar transistor), a bipolar transistor and a diode, which simultaneously exhibit a high breakdown voltage and a high current capacity. More specifically, the present invention relates to a semiconductor device structure including a vertical drain drift layer and the method of manufacturing the semiconductor device.
The semiconductor devices may be roughly classified into a lateral device, that arranges the main electrodes thereof on one major surface, and a vertical device that distributes the main electrodes thereof on two major surfaces facing opposite to each other. In the vertical device, a drift current flows in the ON-state of the device and depletion layers expand in the OFF-state of the device both in the thickness direction of the substrate thereof (vertically). FIG. 9 is a cross sectional view of a conventional planar-type vertical n-channel MOSFET. Referring now to FIG. 9, the vertical MOSFET includes an n+-type drain layer 11 with low electrical resistance; a drain electrode 18 in electrical contact with the back surface of n+-type drain layer 11; a highly resistive n-type drain drift layer 12 on n+-type drain layer 11; p-type base regions 13 (p-type well regions or channel diffusion regions) formed selectively in the surface portion of drain drift layer 12; a heavily doped n+-type source region 14 formed selectively in the surface portion of p-type base region 13; a heavily doped p+-type contact region 19 formed selectively in the surface portion of p-type base region 13; a gate insulation film 15 on the extended portion of p-type base region 13 extended between-type drain drift layer 12 and n+-type source region 14; a polysilicon gate electrode layer 16 on gate insulation film 15; and a source electrode 17 in common contact with n+-type source region 14 and p+-type contact region 19.
Highly resistive n-type drain drift layer 12 provides a vertical drift current path in the ON-state of the MOSFET and is depleted in the OFF-state of the MOSFET to increase the breakdown voltage. Shortening the current path in n-type drain drift layer 12 is effective to substantially reduce the on-resistance (the resistance between the source and the drain) of the MOSFET, Since the drift resistance is reduced. However, the shortening the current path in n-type drain drift layer 12 narrows the expansion width of the depletion layer expanding from the pn-junction between p-type base region 13 and n-type drain drift layer 12. Since the depletion electric field strength soon reaches the maximum electric field (critical electric field) of silicon due to the narrowed expansion width of the depletion layer, the breakdown voltage (the voltage between the drain and the source) of the MOSFET is reduced. Although a high breakdown voltage is obtained by thickening n-type drain drift layer 12, thick n-type drain drift layer 12 inevitably causes on-resistance increase, that further causes on-loss increase. In other words, there exists a tradeoff relation between the on-resistance (current capacity) and the breakdown voltage. The tradeoff relation between the on-resistance and the breakdown voltage exists also in the other semiconductor devices such as IGBT""s, bipolar transistors and diodes.
European Patent 0 053 854, U.S. Pat. No. 5,216,275, U.S. Pat. No. 5,438,215, Japanese Unexamined Laid pen Patent Application H09-266311 and Japanese Unexamined Laid Open Patent Application H10-223896 disclose semiconductor devices, which include an alternating conductivity type layer formed of heavily doped n-type regions and heavily doped p-type regions alternately arranged with each other to obviate the problems described above.
FIG. 10 is a cross sectional view of the vertical MOSFET disclosed in U.S. Pat. No. 5,216,275. The vertical MOSFET of FIG. 10 is different from the vertical MOSFET of FIG. 9 in that the vertical MOSFET of FIG. 10 includes a drain drift layer 22, that is not of one conductivity type but of alternating conductivity types and formed of n-type drift current path regions 22a and p-type partition regions 22b alternately arranged with each other. Even if the impurity concentrations in the alternating conductivity type layer are high, a high breakdown voltage will be obtained, since depletion layers expand laterally, in the OFF-state of the device, from multiple pn-junctions extending vertically across the alternating conductivity type layer.
Drain drift layer 22 is formed in the following way. An n-type layer is grown epitaxially on an n+-type drain layer 11 as a substrate. Trenches are dug through n-type layer down to n+-type drain layer 11, leaving n-type drift current path regions 22a. Then, p-type partition regions 22b are epitaxially grown selectively in the trenches. Hereinafter, the semiconductor device including a drain drift layer of alternating conductivity types as described above will be referred to sometimes as the xe2x80x9csuper-junction semiconductor devicexe2x80x9d.
Detailed dimensions of the super-junction semiconductor device disclosed in U.S. Pat. No. 5,216,275 are as follows. The thickness of drain drift layer 22 is described with a breakdown voltage VB by 0.024VB1.2 (xcexcm). When the thickness of n-type drift current path regions 22a and the thickness of p-type partition region 22b are the same b and the impurity concentrations in n-type drift current path regions 22a and p-type partition region 22b are the same N, the impurity concentration and the thickness b are related with each other by N=7.2xc3x971016VB0.2b (cm3). When VB is 800 V and b is 5 xcexcm, the impurity concentration N is 1.9xc3x971016 cm3. Since the impurity concentration in the conventional drain drift layer of one conductivity type is around 2xc3x971014 cm3, the drain drift layer of alternating conductivity types facilitates realizing a high impurity concentration therein, reducing the on-resistance and providing the semiconductor device with a high breakdown voltage.
However, the trenches for forming p-type partition regions 22b are narrow and deep. It is difficult for the presently available selective etching techniques to dig the trenches with such a large aspect ratio, and it is difficult for the presently available epitaxial growth techniques to grow a high-quality single crystal layer in such a narrow and deep trench. Since it is required to further narrow and thicken each region in the drain drift layer of alternating conductivity types to obtain a higher breakdown voltage, the aspect ratio of the trenches for forming the p-type partition regions should inevitably be larger. Obviously, the use of trenches for forming the p-type partition regions causes a limit for obtaining a higher breakdown voltage and, therefore, is not so practical.
In view of the foregoing, it is an object of the invention to provide a semiconductor device including a improved drain drift layer structure of alternating conductivity types, that is easy to manufacture. It is another object of the invention to provide a semiconductor device that facilitates realizing a high current capacity and a high breakdown voltage. It is still another object of the invention to provide a method of manufacturing the semiconductor device.
According to an aspect of the present invention, there is provided a semiconductor device including: an alternating conductivity type layer formed of vertical first regions of a first conductivity type and vertical second regions of a second conductivity type; the vertical first regions and the vertical second regions being alternately arranged with each other; each of the vertical first regions or each of the vertical second regions being formed of epitaxially grown layers laminated with each other; and each of the vertical second regions or each o the vertical first regions being formed of buried diffusion unit regions connected vertically with each other.
Since the vertical first regions or the vertical second regions are built in by connecting buried diffusion unit regions vertically, the impurity concentration in the vertical first regions or the vertical second regions exhibits almost isotropic distributions around the scattered diffusion centers aligned vertically. Although the impurity concentration distribution in the vertical first regions or the vertical second regions is not uniform, pn-junction planes between the vertical first regions and the vertical second regions are almost flat. Since the narrow vertical first regions, which provide a vertical current path in the ON-state of the semiconductor device, can be doped heavily, the alternating conductivity type layer according to the invention facilitates realizing a high current density. Since the vertical second regions are depleted in the OFF-state of the semiconductor device by the depletion layers expanding laterally from the pn-junctions on both sides thereof, alternating conductivity type layer according to the invention facilitates realizing also a high breakdown voltage.
The vertical first regions and the vertical second regions having the structures as described above are formed according to the invention by repeating the step of laminating epitaxially grown layer with the step of implanting impurity ions of one conductivity type into the diffusion centers in the surface portion of the latest epitaxially grown layer interposed between the steps of laminating and by thermally diffusing the impurities stored between the epitaxially grown layers at once to connect the buried diffusion unit regions vertically with each other. The manufacturing method according to the invention facilitates narrowing and elongating the vertical first regions and the vertical second regions.
Since it is not necessary to dig trenches with a large aspect ratio by etching nor to epitaxially grow Iayers selectively in the trenches, the manufacturing method according to the invention facilitates easy manufacture of the super-junction semiconductor device. Since it is enough to implant impurity ions of only one conductivity type, the manufacturing method according to the invention facilitates confining concentration distributions within a narrow range and reducing the manufacturing steps. Therefore, the manufacturing method according to the invention facilitates forming an alternating conductivity type layer including narrow regions alternately arranged with each other and, therefore, providing a practical vertical super-junction semiconductor device.
The alternating conductivity type layer and the method of manufacturing the alternating conductivity type layer according to the invention are applicable not only to the vertical semiconductor devices distributing the main electrodes thereof on both major surfaces of the semiconductor chip facing opposite to each other but also to the lateral semiconductor devices having the main electrodes thereof on one major surface of the semiconductor chip. The invention is applicable to the semiconductor device including an alternating conductivity type layer shaped with a letter V and to manufacturing the semiconductor device.
The alternating conductivity type layer according to the invention includes vertical first regions or vertical second regions formed in the laminate of epitaxially grown layers by three-dimensionally driving buried diffusion unit regions by thermally diffusing the impurities at once from the impurity sources (diffusion centers) formed in advance between the epitaxially grown layers. The vertical first regions or the vertical second regions may be extended obliquely to the major surface of the semiconductor device. The alternating conductivity type layer may three-dimensionally extend zigzag or helically. The zigzag arrangement or the helical arrangement of the alternating conductivity type layer facilitates providing a drift current path longer than the thickness of the alternating conductivity type layer and, therefore a higher breakdown voltage. The vertical first regions or the vertical second regions maybe extended obliquely by connecting the buried diffusion unit regions displaced laterally for a certain distance from an epitaxially grown layer to another epitaxially grown layer. Although it is impossible in principle for the trench structure to built in oblique drift current path regions or oblique partition regions in the alternating conductivity type layer, the method of connecting the buried diffusion unit regions according to the invention facilitates forming oblique drift current path regions or oblique partition regions in the alternating conductivity type layer. Although the method of connecting the buried diffusion unit regions according to the invention is not so effective to form an active region nor a passive region of the semiconductor device, the method of connecting the buried diffusion unit regions according to the invention is applicable to forming drift region internal vertical current path regions and pn-isolation regions. The method of connecting the buried diffusion unit regions according to the invention is applicable to the vertical wiring between the devices laminated in a semiconductor chip.
According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device including an alternating conductivity type layer formed of vertical first regions of a first conductivity type and vertical second regions of a second conductivity type, the vertical first regions and the vertical second regions being alternately arranged with each other, each of the vertical first regions or each of the vertical second regions being formed of epitaxially grown layers laminated with each other, and each of the vertical second regions or each of the vertical first regions being formed of buried diffusion unit regions connected vertically with each other, the method including the steps of: (a) forming an epitaxially grown layer doped relatively lightly on a substrate; (b) selectively implanting impurity ions of the second conductivity type or the first conductivity type into diffusion centers in the surface portion of the epitaxially grown layer; (c) repeating the steps (a) and (b) to form a laminate including a desired number of the diffusion center aligned vertically; and (d) thermally diffusing the implanted impurity ions from the diffusion centers to connect the buried diffusion unit regions vertically with each other.
Alternatively, there is provided a method of manufacturing a semiconductor device including an alternating conductivity type layer formed of vertical first regions of a first conductivity type and vertical second regions of a second conductivity type, the vertical first regions and the vertical second regions being alternately arranged with each other, each of the vertical first regions or each of the vertical second regions being formed of epitaxially grown layers laminated with each other, and each of the vertical second regions or each of the vertical drift current path regions being formed of buried diffusion unit regions connected vertically with each other, the method including the steps of: (a) selectively implanting impurity ions of the second conductivity type or the first conductivity type into diffusion centers in the surface portion of a substrate; (b) forming an epitaxially grown layer doped relatively lightly on the substrate; (c) selectively implanting impurity ions of the second conductivity type or the first conductivity type into diffusion centers in the surface portion of the epitaxially grown layer; (d) repeating the steps (b) and (c) to form a laminate including a desired number of the diffusion centers aligned vertically; and (e) thermally diffusing the implanted impurity ions from the diffusion centers to connect the buried diffusion unit regions vertically with each other.
Layers with low electrical resistance may be formed to laterally connect the thus formed drift current path regions. In the steps of forming an epitaxially grown layer, the conductivity type of the epitaxially grown layers may be opposite to the conductivity type of the substrate.
The ion implantation method facilitates positioning the maximum concentration points (the impurity sources) at the depth corresponding to the average range from the surface of the area through which impurity ions are implanted, and lowering the local impurity concentrations in the surface portions, through which the impurity ions are implanted. Since the ion implantation method facilitates keeping the boundary planes between the epitaxially grown layers clean, the crystal qualities in the respective laminated epitaxially grow layers are equalized, the influences of auto-doping are reduced, and the impurity concentrations in epitaxially grown layers, which determine the conductivity type of the epitaxially grown layers, are equalized. Since the crystal qualities in the epitaxially grown layers are impaired more with increasing number of the laminated epitaxially grown layers, the ion implantation method is very useful for manufacturing the devices including an active region or a passive region formed on the uppermost epitaxially grown layer. In some cases, it is appropriate to form layers with low electrical resistance in the uppermost epitaxially grow layer and to form an active region of the device in the epitaxially grown layers on the side of the substrate, thereon the epitaxially grown layers are formed.
Although defect (amorphous) layers are caused in the surface portions corresponding to the locations of the windows, through which the impurity ions are implanted, the defect layers do not pose any problems, since the defect layers are annealed easily to be crystallized again by the final heat treatment. As the vertical regions in the alternating conductivity type layer are narrower, a higher breakdown voltage is obtained. To obtain a higher breakdown voltage, a narrower window is used for the ion implantation. Even when some arrays of point defects are remaining, the remaining point defects do not pose any problem on the drift current path regions, since the point defects are confined in narrow regions beneath the surface portions corresponding to the windows, through which impurity ions are implanted.
Advantageously, the step of non-selectively implanting impurity ions of the first conductivity type or the second conductivity type in the entire surface portion of the epitaxially grown layer is inserted between the preceding step of forming an epitaxially grown layer and the succeeding step of forming an epitaxially grown layer. It is appropriate to non-selectively implant the impurity ions of the same conductivity type with that of the epitaxially grown layers. The non-selective implantation, that increases or compensates the impurity concentration in the epitaxially grown layers, facilitates increasing the impurity concentrations in the alternating conductivity type layer and, therefore, increasing the current capacity. The initial conductivity type of the epitaxially grown layers at the time of the epitaxial growth thereof may be n-type or p-type, since the final impurity concentrations in the alternating conductivity type layer are determined by the concentration of the non-selectively implanted impurity ions of the first conductivity type or the second conductivity type. Preferably, the impurity concentration in the epitaxially grown layers is between 2xc3x971013 cm3 and 1xc3x971016 cm3. The preferable impurity concentration facilitates suppressing impurity concentration distribution and realizing a high breakdown voltage and a high current capacity.
Preferably, the steps of implanting impurity ions of the first conductivity type and the second conductivity type are conducted using ion implantation facilities of the same series supplied from the same manufacturer. The concentration distribution is further reduced.
More preferably, the steps of implanting ions of the first conductivity type and the steps of implanting ions of the second conductivity type are conducted using respective ion implantation facilities of the same type supplied from the same manufacturer.
Most preferably, the steps of implanting ions of the first conductivity type and the steps of implanting the ions of the second conductivity type are conducted using the same ion implantation facility.